In DRAMS, respective memory cells may e.g. consist substantially of capacitors. The memory cells/capacitors are connected to bit lines which serve to transmit a data value to be read out from the memory cell or a data value to be read into the memory cell.
On the reading out of a memory cell, an access transistor that is connected with the capacitor of a memory cell is connected through by the activation of a word line, and the charge condition stored in the capacitor is applied to the bit line.
Subsequently, the weak signal emanating from the capacitor is amplified by a read amplifier (“sense amplifier”). The read amplifier comprises complementary signal inputs. The bit lines connected to these signal inputs are referred to as bit line and complementary bit line.
In today's DRAMS, the read amplifiers may be used as “divided parts” so as to save chip space. In so doing, a read amplifier is used both during the reading out of a memory cell positioned at the left and a memory cell positioned at the right side along respective bit lines associated with a read amplifier (hence, the read amplifiers are used as so-called “shared sense amplifiers”).
Prior to the reading out of the memory cells, the corresponding bit line sections, i.e. the corresponding sections of the non-complementary bit line and of the complementary bit line, are, by so-called precharge/equalize circuits that are connected with the bit lines, precharged to the same potential, which corresponds to half the voltage of a bit line in a logic high state (i.e., to VBLH/2). This ensures that—prior to the reading out of data—no differences occur between the potential of the section of the bit line and the section of the corresponding complementary bit line, which otherwise might superimpose the small amount of charge transferred by the capacitor of a memory cell to the bit lines during reading out. Directly prior to the reading out of the memory cells the precharge-/equalize circuits which are connected to the bit line sections that are adapted to be connected with the memory cell to be read out are switched off.
Known DRAMS moreover comprise isolation circuits with isolation transistors, which serve to decouple the read amplifier during the reading out of the memory cells from the side/bit line sections that is/are not connected to memory cells to be read out.
Each isolation circuit e.g. might consist of two NMOS-FETs, the source-drain paths of which are adapted to interrupt the corresponding bit line sections.
With known DRAMs, outside the read and write cycles, respective bias voltages are applied to the gates of the isolation transistors of the isolation circuits. These bias voltages might e.g. correspond to a voltage (VINT) generated internally on the DRAM chip.
Directly prior to the reading out of a memory cell the side of the read amplifier that is connected with memory cells not to be read out is coupled off the respective bit line section(s) by the gates of the respective isolation transistors positioned on this side of the read amplifier being put to ground. Simultaneously, the other side of the read amplifier may be coupled in an improved manner to the respective bit line section(s) by the gate voltage that is applied to the gates of the isolation transistors positioned on the other side of the read amplifier being slightly increased e.g. from its above initial value VINT to a voltage value VPP.
The actual reading out of the memory cell is initiated shortly thereafter by appropriate word line signals connecting through the access transistors that are connected with the memory capacitors. Subsequently, appropriate activating voltages are applied to the read amplifier, whereupon the read amplifier amplifies the potential differences transferred from the memory capacitors to the corresponding bit line sections, and outputs a respective amplified differential signal.
The respective amplified differential signal is transmitted from the read amplifier to respective local data lines, the local data lines being adapted to be coupled to the read amplifier by respective transistors (“bit switches”).
To connect the local data lines to the read amplifier, a control signal CSL applied to the gate of the above transistors (bit switches) is driven to a logic high state (e.g., to the above voltage VINT), such that the respective transistors (bit switches) are connected through.
The above amplified differential signal is transmitted from the local data lines to respective global data lines, and to a further amplifier (so-called “secondary sense amplifier”) for further amplification.
The driver circuit for the above control signal CSL applied to the gate of the above transistors (bit switches) might be a simple inverter which allows switching of the CSL signal between 0V and e.g. VINT.
For the above reading out of memory cells (“read access”), both local data lines (called e.g. LocalData-Line_t and LocalDataLine_c) associated with a respective read amplifier might first be pre-charged to a voltage level of e.g. VBLH (with VBLH e.g. being smaller than VINT).
When CSL is asserted, a first of the above local data lines (e.g. the LocalDataLine_c) might then—depending on the state of the read amplifier—be slowly discharged through the respective bit switch transistor, the resulting differential signal (as said above) being passed on to the above global data lines, and to the above further amplifier (secondary sense amplifier).
To write data onto the memory cells (“write access”), e.g., to write a “0”, a second one of the above local data lines (e.g. the LocalDataLine_t) associated with the above read amplifier might be forced to 0V, whilst the other one of the above local data lines (e.g. the Local-DataLine_c) might still be held at the above pre-charge voltage level of e.g. VBLH.
The logic low voltage level of the above LocalDataLine_t is forced onto a respective one of the (pair) of bit lines associated with the respective read amplifier, which causes the read amplifier to flip.
As can be seen from the above description, the bit switches are operated bi-directionally (in a first direction for a read, and in a second direction for a write access).
For a write access, it must be ensured that the bit switches drive sufficient current. Otherwise, the read amplifier cannot be flipped fast enough (in particular, within the time period when CSL is in a logic high state).
However, during a read access, excessive current drive of the bit switches might disturb the signals on the bit line pair associated with the respective read amplifier, potentially causing the read amplifier to switch, and destroying the information to be read out of the memory cells.
To overcome the above problems, the bit switches have to be sized appropriately, and—potentially—the CSL signal has to be delayed, leading to a decreased performance, in particular, to an increase in the respective (total) access times for the respective memory.
It is therefore an object of the invention to provide an improved semiconductor memory and an improved method for operating a memory. In particular, it is an object of the invention to provide a semiconductor memory with an improved performance compared with semiconductor memories according to the state of the art.